Various etching processes are used in the fabrication of semiconductor devices. Such etching processes are used to control and maintain critical dimensions of various device structures such as, for example, transistors, capacitors, and interconnects. As semiconductor devices become more integrated and miniaturized, the maintenance and control of such critical dimensions of device structures increases in importance.
During the formation of semiconductor devices, such as dynamic random access memories (DRAMs), static random access memories (SRAMs), microprocessors, etc., various layers are etched to form insulating structures, e.g., openings, used for various purposes. Such purposes may include the formation of capacitor structures, contact structures, interconnect structures, etc. For example, with respect to capacitor structures, it is often required that a conductive structure be deposited on the inner surface of a recess in a dielectric layer.
The profile of such conductive structures is of particular importance, for example, such that desired characteristics are exhibited when further processing is carried out relative to the structure. For example, in many circumstances it is preferred to have openings having near vertical profiles, e.g., at least one wall being near vertical.
For example, with respect to a contact hole or via, a near vertical wall defining the opening into which conductive structure is formed provides a larger area at the bottom of the opening as opposed to an opening defined by walls that are less than vertical. Contact resistance for a contact formed in the opening is sensitive to the area at the bottom of the opening.
Further, for example, with respect to a conductive structure such as a container capacitor illustratively described in U.S. Pat. No. 5,392,189 to Fazan et al., near vertical walls defining a container opening in which a conductive structure is formed provides a significant increase in cell capacitance for a given height of a capacitor structure relative to a container opening defined by walls that are less than vertical. For example, an opening defined with near vertical walls extending from a bottom surface will generally provide a greater surface area upon which an electrode of a capacitor can be formed relative to a recess having sloped walls which are less than vertical.
It is difficult to etch a recess in a dielectric layer that results in walls that are generally near vertical. This is particularly true with respect to high aspect ratio openings. It is known to utilize dry etch plasmas containing fluorocarbons or hydrofluorocarbons to etch oxides, or other dielectric layers, relative to underlying conductive layers, e.g., silicon-containing layers such as doped silicon, polysilicon, or other conductive materials.
After a recess has been formed by a profile-straightening etch, if necessary, the electrode of a container capacitor is formed. But a high-aspect ratio container capacitor in sub-micron geometries suffers from fragility that cannot survive etching and rinsing that expose the exterior surface of the container capacitor. Often, the rinsing causes adjacent container capacitors to collapse due to the surface tension of the rinse solution.